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Organization

Cadence Design Systems, Inc.
Contributors
Sharath AC
Shubham Agarwal
Charles Alpert
Anunay Bajaj
Akshita Bansal
Akshita Bansal
Joseph Bauer
Tom Beckley
Ratnakar Bhatnagar
Manish Chand
Hongpa Che
Pinhong Chen
Daniel Cross
Shupeng Cui
Yun Dai
Ritesh Desai
Aniket Deshmukh
Edson Gomersall
Mehar Gupta
Ruchin Gupta
Steve Harvey
Jitendra Jain
Nitin Jain
Prayes Jain
Harshit Jaiswal
Jags Jayachandran
Rahil Jha
Rahil Jha
Dae-Hun Jung
Ramesh Kamath
Dongchul Kang
Arif Khan
Ji-Hun Kim
Taejin Kim
Rajat Kukreja
Anup kumar
Vishesh Kumar
Keunbong Lee
Yong Liu
Akshay Mankotia
Naresh Mummidivarapu
Mohamed Naeim
Sravasti Nair
John Park
Krunal Patel
Pooja Patel
Vatsal Patel
Ashwin Ramamurthy
Gopi Ranganathan
Heinz Riener
Ajay Sahoo
Shaikh Salehabibi
Ashwani sanwal
Erik Seligman
Shyam Sharma
Sushant Sharma
Dharini SubashChandran
Kumar Subramani
Pratibha Sukhija
Pratibha Sukhija
Yashodhara Tarey
Girish Vaidyanathan
Kilaru Vamsikrishna
Kilaru Vamsikrishna
Session Chairs
Subhendu ROY
Presentations
Engineering Track Poster
A Decade of Evolution in Formal Verification
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
A Novel Methodology for Library Characterization and Modeling Considering Local Layout Effect
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
A Novel Solution for Fast and Efficient Custom Bus Routing with User-defined Reference Wire and Combination of Segmented Bus Option
Back-End Design
Design
Engineering Tracks
Back-End Design
A Systematic Approach to 3D Cutline Exploration and Benchmarking
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Accelerating Automated Custom Layout Creation Through Smart Design Intent Migration
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Advancing Low Power Design in the Era of Rising Energy Footprints: Insights from IEEE 2416 Standard and Future Extensions
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Advancing Power Signoff for High Speed ΔΣADC
Engineering Tracks
IP
Back-End Design
An effective Hierarchical STA solution for closing Large SoC Design
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
An effective Hierarchical Top Scope Signal EM Flow for closing Large SOC Designs
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
An uptick on Automotive Safety Solutions using Cadence Implementation Tools
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Areal and Time Decomposed Phalanx based Dynamic IR-Drop Prediction using DNN(Deep Neural Network) at Earlier stage of Design cycle
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Automated Place and Route based solution for Custom Blocks
Back-End Design
Embedded Systems
Front-End Design
IP
DAC Pavilion Panel
Best of Both Worlds: Bridging the Gaps in Engineering Software for Semiconductors and Systems
Engineering Track Poster
Design Enablement of 2D/3D Power-Thermal Self-Consistent Analysis
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
DVD-aware STA and its silicon correlation results on 10nm test chip
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Elevating BFM Capabilities:
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Enhanced State-Propagation based Vectorless IR-Drop Analysis Emulating Realistic Silicon Behavior
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Executable Tables, 'A Journey from Document to Simulation Capable, Exemplified Using DDR5 '
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Future Proofing Chiplet Testbenches: Resilience in Multiprotocol Era
Back-End Design
Embedded Systems
Front-End Design
IP
Research Panel
Generative AI for Chip Design: Game Changer or Damp Squib?
AI
EDA
Special Session (Research)
Invited: The Role of EDA as Chips Transform Into 3D Systems
EDA
Late Breaking Results Poster
Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration
Engineering Track Poster
Matched Placement and Routing using Synchronized Unit Cell Array
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Modeling Optimal Number of Tap-points for Flexible H-tree During Clock Tree Synthesis
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Solving Memory Subsystem Verification Challenges for Multi-Instance Designs
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Systematic Verification Framework for Memory Subsystem Ensuring Reliability and Robustness
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Technology and IP Scaling Beyond 5nm
Engineering Tracks
IP
Back-End Design
Timing Robustness: A Way forward for analyzing timing-voltage sensitive paths for accounting IR-Drop Variations
Back-End Design
Design
Engineering Tracks
Research Panel
Why Is EDA Playing Catchup to Disruptive Technologies Like AI? What Can We Do to Change This?
AI
EDA
Sessions
Research Manuscript
Charting a Course to Navigate Irregular Data Access in Graph Neural Networks and Beyond!
AI
Design
AI/ML Architecture Design