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Autonomous Power Sequence validation solution for I/O using Solido Design Environment
DescriptionThe characterization of input/output (IO) devices is complex and time-consuming process due to the multiple supplies involved, such as VDD and VDDE, which ramp up at different rates and in different orders. This is particularly important in the context of modern complex IO design, which often require rigorous validation to ensure reliable and robust operation.

This complexity can be addressed with automation scripts that enable the efficient generation of various validation scenarios in characterization process. In this way, designers can save significant time and effort, while also improving the accuracy and completeness of the validation process

To achieve this, the automation scripts is designed to automatically generate series of tests that cover a range of supply ramp rates and orders. The scripts can be customized to the specific requirements of the IO device being characterized, and by addition to Solido Design Environment can incorporate a variety of simulation and analysis techniques available, such as Monte Carlo analysis and sensitivity analysis.

The addition of an automation script for IO device characterization to the Solido Design Environment represents a significant technical advance in the design and verification of analog and mixed-signal ICs, with important implications for efficiency, accuracy, and reliability.
Event Type
Engineering Track Poster
TimeTuesday, June 255:26pm - 5:27pm PDT
LocationLevel 2 Exhibit Hall
Topics
Back-End Design
Embedded Systems
Front-End Design
IP