Presentation
Systematic Verification Framework for Memory Subsystem Ensuring Reliability and Robustness
DescriptionThe vertical segments across IoT, data centers, AI, networking, autonomous vehicles, cryptocurrency infrastructure are creating data requirements explosion. New standards, emerging at lightning speeds, are battling the never-ending thirst for low power, high speed and throughput. With the increase in complexity, the verification effort is also increasing exponentially. Multiple DRAM memory vendors and wide varieties of memory are growing challenges as each vendor have their own unique timing parameter types/ values and configuration register values. Ensuring the correctness of timing parameter values and registers so that the DDR Controller, DDR PHY, and the DRAM device operate in sync is a huge and error-prone task. To make this effort error-free, we have developed an automated and scalable solution where the verification features of DFI and Memory are integrated and synced to reduce the verification efforts, fast time to market, and no silicon escape.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP