Presentation
An efficient QA methodology for SRAM libraries
DescriptionAt Renesas, we develop compact and low-power SRAMs for our products. For our SRAM library development, we produce and verify all 10,000+ memory instances generated by our Memory Compiler.
All SRAM IPs must be validated across a wide range of process, voltage, and temperature (PVT) conditions, as well as multiple views and formats for consistency and correctness, including logical, physical, timing, SPICE, and other views. This requires significant time and effort.
To enhance IP QA process in terms of efficiency and coverage, Renesas has built an SRAM IP QA methodology in collaboration with Siemens' Solido Crosscheck. This methodology includes several custom checks from Renesas, in addition to standard SRAM and IP checks. It covers all relevant front-end and back-end design views for IP production and integration workflows, and enables Renesas to fully validate IPs in significantly less time than before.
In this paper, we will discuss Renesas' efficient SRAM IP QA methodology. Within this methodology, we will also highlight key QA checks for SRAM validation, the importance of such rules, and provide insight into QA efficiency and coverage of the flow.
All SRAM IPs must be validated across a wide range of process, voltage, and temperature (PVT) conditions, as well as multiple views and formats for consistency and correctness, including logical, physical, timing, SPICE, and other views. This requires significant time and effort.
To enhance IP QA process in terms of efficiency and coverage, Renesas has built an SRAM IP QA methodology in collaboration with Siemens' Solido Crosscheck. This methodology includes several custom checks from Renesas, in addition to standard SRAM and IP checks. It covers all relevant front-end and back-end design views for IP production and integration workflows, and enables Renesas to fully validate IPs in significantly less time than before.
In this paper, we will discuss Renesas' efficient SRAM IP QA methodology. Within this methodology, we will also highlight key QA checks for SRAM validation, the importance of such rules, and provide insight into QA efficiency and coverage of the flow.
Event Type
Engineering Track Poster
TimeTuesday, June 255:39pm - 5:40pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP