Presentation
SSN and EMA Bus Path Automation
DescriptionAs designs grow larger and more complex, more advanced Design for Test (DFT) approaches continue to be developed to keep up with the capacity required. One of these approaches is "Streaming Scan Network" (SSN), which is aimed at distributing scan test data across the entire design through a bus structure and allows for easy scalability with independent scan channels in each block/core of the design. Another feature used as part of DFT is the "Early Margin Adjust" (EMA) capability of memory macros, which allows for adjusting timing margins of the memory by setting register values during test bring-up. Both functions require distribution to / through all hierarchical blocks in the design, which historically has been handled manually, with the Physical Design team determining bus traversal paths through blocks and feeding that back to the DFT team for implementation. This approach can be extremely time consuming due to the complexities of chip floorplans introduced by rectilinear shapes and hierarchical block reuse, so is often deferred, risking late-breaking issues. This presentation details a set of systems designed to automate generation of paths through a design, providing access to optimized bus distribution orders for DFT implementation, starting from the first floorplans.
Event Type
Engineering Track Poster
TimeTuesday, June 255:11pm - 5:11pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP