Presentation
Accelerated Design Rule Learning for Silicon Photonics
DescriptionThe amount of data generated in 2025 is estimated to be 181 zettabytes (181,000,000,000,000,000,000,000 bytes). To accommodate this, the size of data centers keeps expanding, putting different servers of the same data center several miles away from each other. Optical fibers are a necessity between servers and leveraging Silicon Photonics comes into play. With only about 15 years of learning ("All-silicon active and passive guided-wave components for λ = 1.3 and 1.6 µm": https://ieeexplore.ieee.org/document/1073057), Silicon Photonics doesn't have as much legacy information as CMOS2 (~ 75 years: https://en.wikipedia.org/wiki/History_of_the_transistor). We can't afford to wait another 50 years, so how do we accelerate this learning pace?
To face this challenge, we will discuss strategies such as: anticipating design constraints based on FMEA analysis in order to accelerate design timeline, design compaction to support higher packaging density, minimizing wafer scraps and improvement of wafer yield.
This presentation will discuss our research approach, the hurdles we encountered and how we handled them as well as the current limits and our future steps.
FMEA: Failure Mode and Effect Analysis
To face this challenge, we will discuss strategies such as: anticipating design constraints based on FMEA analysis in order to accelerate design timeline, design compaction to support higher packaging density, minimizing wafer scraps and improvement of wafer yield.
This presentation will discuss our research approach, the hurdles we encountered and how we handled them as well as the current limits and our future steps.
FMEA: Failure Mode and Effect Analysis
Event Type
Engineering Track Poster
TimeTuesday, June 255:38pm - 5:39pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP