Presentation
Systematic Flow on AC Scan Timing/ATPG Constraint Generation
DescriptionDFT engineers take efforts on high quality SDC delivery in limited schedule for timing analysis and ATPG. To meet the schedule, engineer often got quality loss on false path consistency due to limited schedule or human error causing coverage loss or time wasted on timing violation review. APR timing closure progress will also be impacted. Moreover, function constraint is often updated during timing closure progress. Function constraint cannot be directly used in AC scan and referencing timing report to prepare AC scan constraint often sacrifice test coverage. Preparing AC scan constraint often takes time and rely on DFT engineer's experience to ensure the constraint quality.
We provided a systematic flow to generate AC scan timing and ATPG constraint dealing with clock structure difference, unsupported description due to ATPG tool limitation, multiple test mode for ATPG, and add-on/redundant timing exception due to Scan structure. The flow helps map AC scan clocks to function clocks and generate AC scan timing and ATPG constraints efficiently.
We provided a systematic flow to generate AC scan timing and ATPG constraint dealing with clock structure difference, unsupported description due to ATPG tool limitation, multiple test mode for ATPG, and add-on/redundant timing exception due to Scan structure. The flow helps map AC scan clocks to function clocks and generate AC scan timing and ATPG constraints efficiently.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP