Presentation
Matched Placement and Routing using Synchronized Unit Cell Array
DescriptionIn Analog Design, matching is very critical to ensure yield, as even a few millivolts difference between neighboring devices can break the circuit. In this paper, we present a flow for matched placement and routing using Group Arrays. Group Arrays are repeated pattern of synchronized unit cells. The unit cell is repeated in patterns in the design such that the parameters (width, length etc.) of each unit is same as that of others in the array. To create repeated design patterns, number of rows and columns can be altered along with spacing between cells and orientation pattern of the cells. Each unit cell comprises of devices and routing, individually or in combination. As Group Array supports synchronous editing, changes made to unit cell is replicated across all cells. If the specifications are modified, then design changes can be done very quickly by working on the unit cells, simplifying ECOs and DRC corrections. The placement and routing of an entire block can be done efficiently using Group Array and is shown in this paper.
Event Type
Engineering Track Poster
TimeTuesday, June 255:31pm - 5:32pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP