Presentation
Machine-Learning-Driven Floorplan-Aware Power Delivery Network Co-Planning
DescriptionEnabling new applications such as autonomous driving or car architectures with centralized ECUs, heterogeneous systems-on-chip (SoCs) with multiple CPUs, multi-level memory hierarchies, various co-processors and hardware accelerators is becoming a key architectural paradigm. Such highly dense automotive SoCs implemented in advanced CMOS technologies are sensitive to process-voltage-temperature variations and other physical disturbances. To mitigate increasing sensitivity challenges of logic gates and memories to transient supply noise, temperature effects and process variations, robust-enough power-delivery networks (PDNs) must be implemented. However, PDN development is facing its own challenges such as late-stage sign-off during the SoC's development cycle, long simulation times, computationally intensive simulations, and late discovery of voltage-drop and electromigration violations when fixes are expensive to implement. Furthermore, PDNs are typically initially defined without considering the package. To overcome these limitations, we propose a machine-learning-driven floorplan-aware power-co-planning methodology using Ansys' OptiSlang that shifts left the PDN development to the prototyping (architecture) abstraction level and enables automation of PDN die-package co-design and verification. Our solution transforms PDN development from a process that produces a couple of simulation results using more than 10 experts in several months into one that compares more than 1000 results using a single expert in a few days.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP