Presentation
Shift-left methodology to identify invalid voltage level shifts & validate signal pins' P/G association in IPs/Block's UPF & .LIB views using PERC's static-voltage tracing mechanism
DescriptionSeveral silicon failures were identified in NXP SOCs due to incorrect voltage level shifting caused either by incorrect Liberty/UPF views generated for the IPs or issues in design practices. Incorrectness in Liberty/UPF views propagates through the design and shields the detection of discrepancies that might arise due to invalid voltage level shifts at various stages of the design cycle.
A two-stage PERC based validation mechanism, based on Calibre-PERCs static voltage tracing mechanism, was added to NXPs PERC solution in the form of following checks:
1) IP/Block level - Check the sanctity of the UPF/.lib file w.r.t. associated Power & Ground domains for IO (signal) pins. This check helps in identifying issues at IP level.
2) SOC level - Checks all the nets with Power Level Shifts and verifies presence of a valid Level Shifter on the identified interface net. This is an umbrella check covering all the scenarios of invalid Power Level shifts across the design irrespective of hierarchy.
Efficacy of the checks was established both at IP & SOC level (#1 & #2) respectively making it a part of NXPs standard IP & SOC verification process. Since the checks' validation process can start as early as at IP level, the check contributed to NXPs Shift-Left initiative.
A two-stage PERC based validation mechanism, based on Calibre-PERCs static voltage tracing mechanism, was added to NXPs PERC solution in the form of following checks:
1) IP/Block level - Check the sanctity of the UPF/.lib file w.r.t. associated Power & Ground domains for IO (signal) pins. This check helps in identifying issues at IP level.
2) SOC level - Checks all the nets with Power Level Shifts and verifies presence of a valid Level Shifter on the identified interface net. This is an umbrella check covering all the scenarios of invalid Power Level shifts across the design irrespective of hierarchy.
Efficacy of the checks was established both at IP & SOC level (#1 & #2) respectively making it a part of NXPs standard IP & SOC verification process. Since the checks' validation process can start as early as at IP level, the check contributed to NXPs Shift-Left initiative.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP