Presentation
Empowering Early-Stage Design: An Automated Solution for Die Size Estimation and IO Ring Creation
DescriptionIn the dynamic landscape of electronics design, the escalating market demand for new devices has led to increased complexity in evaluating and comparing configurations and feature requirements based on customer needs and packages. This intricacy poses a challenge for designers, making decision-making in this domain a laborious task. In the initial stages of product development, designers' endeavor to assess the cost of the new device by estimating its die size (silicon area) and exploring various configuration possibilities. Furthermore, a strategic focus on optimizing PPA (Power, Performance, and Area) at a given process node involves increasing performance (MHz) and adding memories, leading to higher power consumption and larger die sizes. Ensuring compatibility with a target package (E.g., QFP: Quad Flat Package) introduces complexities like complex ground rings and down-bondings. Addressing these challenges necessitates highly efficient, predictable, and fast solutions. Presently, there is a lack of automated tools to tackle this problem. In this paper, we propose an automated solution to address aforementioned challenges, facilitating informed decisions at the outset of the design process. This work aims to prevent late surprises and enhance overall predictability.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP