Presentation
AI-Enhanced Automated Optimization Workflow for HBM Interconnect on Interposer
DescriptionWith the rise of generative AI applications, there is a growing demand for high-bandwidth memory in AI/GPU chips, and interposer designs like UCIE for D2D and SOC to HBM interconnects are increasingly popular for chiplets interconnection. Interposer designs face unique challenges like small trace width, high interconnect density, and the absence of a solid plane. These challenges make traditional SI flow time consuming and lack of silicon-based material consideration. An efficient and accuracy pre-layout analysis flow is very urgently needed.
This paper proposes an efficient interposer high-speed design simulation and optimization flow. This flow is driven by optiSLang, allowing for the configuration of design parameters and objectives. By leveraging various AI/ML algorithms, the solution space is explored to identify the optimal design. This flow operates as a closed-loop automatic iterative optimization process.
In summary, this paper presents an automated interposer pre-layout design simulation and optimization flow. The proposed flow enhances accuracy, speed, and realism compared to traditional manual approaches, and the validation results demonstrate its effectiveness and applicability.
This paper proposes an efficient interposer high-speed design simulation and optimization flow. This flow is driven by optiSLang, allowing for the configuration of design parameters and objectives. By leveraging various AI/ML algorithms, the solution space is explored to identify the optimal design. This flow operates as a closed-loop automatic iterative optimization process.
In summary, this paper presents an automated interposer pre-layout design simulation and optimization flow. The proposed flow enhances accuracy, speed, and realism compared to traditional manual approaches, and the validation results demonstrate its effectiveness and applicability.
Event Type
Engineering Track Poster
TimeTuesday, June 255:04pm - 5:05pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP