Presentation
Balancing Power and Performance: The Hybrid Clock Network Approach for Network on chips
DescriptionIn the rapidly evolving landscape of technology, the pursuit of high-performance systems has become increasingly essential. With the growing complexities in chip design, achieving a harmonious balance between Power, Performance, and Area (PPA) – the foundational pillars of contemporary chip architecture – presents formidable challenges. Traditional clock methodologies such as clock tree synthesis, clock mesh, and multi-source clock tree synthesis have proven inadequate in addressing the intricacies of modern chip design. Recognizing these limitations, we introduce the innovative Hybrid Clock Network technique, a customized approach designed to construct robust clock networks within Network On Chips (NoC).
Our technique has yielded remarkable improvements in clock quality when compared to conventional clock tree methodologies. Notably, our results showcase a 41.66% reduction in latency, a 43.75% enhancement in skew, a 14.22% decrease in clock power consumption, and an overall 12.46% reduction in total power consumption. Additionally, our approach has conserved 11.55% of routing resources, reduced the clock buffer count by 16.2%, and streamlined the clock depth from 23 to 19 levels. These compelling findings underscore the efficacy of our proposed technique in significantly enhancing critical PPA metrics. The Hybrid Clock Network technique represents a breakthrough in addressing the challenges of contemporary chip design, offering a promising path forward in the pursuit of high-performance systems.
Our technique has yielded remarkable improvements in clock quality when compared to conventional clock tree methodologies. Notably, our results showcase a 41.66% reduction in latency, a 43.75% enhancement in skew, a 14.22% decrease in clock power consumption, and an overall 12.46% reduction in total power consumption. Additionally, our approach has conserved 11.55% of routing resources, reduced the clock buffer count by 16.2%, and streamlined the clock depth from 23 to 19 levels. These compelling findings underscore the efficacy of our proposed technique in significantly enhancing critical PPA metrics. The Hybrid Clock Network technique represents a breakthrough in addressing the challenges of contemporary chip design, offering a promising path forward in the pursuit of high-performance systems.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP