Presentation
Automated Floorplan Scaling Solutions and Framework
DescriptionConventional hierarchical design planning flows are neither runtime efficient nor resource efficient for a) quick floorplan porting during process node evaluation and library bring up with minimal dependency or b) what-if exploration to hasten block convergence with improved local FP optimization and identify critical limiters for different partition layout topologies. The scaling framework is a one-stop solution capable of operating on bare minimum baseline floorplan information to port floorplans even without any netlist or memory collaterals. The Framework can generate basic floorplanning compatible netlist and scaled library memory collateral from baseline floorplans on a different node/library. The framework can also enable evaluation of block convergence recipes and floorplan utilization or frequency sweeps through macro placement techniques including ML macro placement suitably augmented with additional algorithmic pin placement intelligence to retain global context. The framework has evolved to be the de facto early floorplan execution flow, scaling and porting floorplans between libraries, nodes and even foundries, and improving the work model execution efficiency by 16X and resource efficiency by 3X for each partition. The framework has also been a key pillar in block optimization exploration, during later execution milestones, saving 2-4 weeks of convergence efforts on 80% of blocks with pre-configured techniques and strategies.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP