Presentation
Accelerating Automated Custom Layout Creation Through Smart Design Intent Migration
DescriptionWith the semiconductor industry's push to newer process nodes and shorter time to market, analog and custom IC layout creation is turning out to be the bottleneck as it has historically been a highly manual process. Since Analog IPs often stay the same across nodes, the ability to automatically recreate the designs can reduce costly iterations and help designs converge faster.
When the design methodology requirements vary across process nodes, layout porting based on mapping of objects and scaling of sizes and coordinates fails miserably in producing high-quality layout that is design rule correct. Our innovative approach of auto-inferring design intents from source layout and driving automated layout creation in target node solves the layout migration challenge with upwards of 2X boost in productivity.
The schematics on the target node are generated by mapping devices and parameters from the source schematic and optimizing them for the target node using customizable machine learning (ML)-based engines. Schematic-driven layout generates node and design-specific grids to ensure DRC-correct placement and routing, while the migration functionality seeds the target layout with relative placement information from the source layout including device groups, captured as scalable templates, that take updated parameters and instance counts into account. Incremental placer legalizes the placement followed by guard ring and fill cell generation that are specific to target process node. In the last step, routing topology information from the source layout is used to generate routing in the target layout to help meet electrical and parasitic requirements through a combination of automation and migration. The final LVS and DRC-clean layout on the target node is generated in a significantly shorter time compared to manual creation, boosted by the use of existing layout footprint and patterns.
When the design methodology requirements vary across process nodes, layout porting based on mapping of objects and scaling of sizes and coordinates fails miserably in producing high-quality layout that is design rule correct. Our innovative approach of auto-inferring design intents from source layout and driving automated layout creation in target node solves the layout migration challenge with upwards of 2X boost in productivity.
The schematics on the target node are generated by mapping devices and parameters from the source schematic and optimizing them for the target node using customizable machine learning (ML)-based engines. Schematic-driven layout generates node and design-specific grids to ensure DRC-correct placement and routing, while the migration functionality seeds the target layout with relative placement information from the source layout including device groups, captured as scalable templates, that take updated parameters and instance counts into account. Incremental placer legalizes the placement followed by guard ring and fill cell generation that are specific to target process node. In the last step, routing topology information from the source layout is used to generate routing in the target layout to help meet electrical and parasitic requirements through a combination of automation and migration. The final LVS and DRC-clean layout on the target node is generated in a significantly shorter time compared to manual creation, boosted by the use of existing layout footprint and patterns.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP