Presentation
A New Approach to Efficient Prelim Package Generation for Faster SOC Implementation
DescriptionIn the fast-paced semiconductor world, rapid time-to-market is crucial. Traditional SoC development, waiting for fully developed IPs, hinders speed and competitiveness. This presentation introduces the concept of preliminary IP CAD views, generated as soon as IP specifications are defined. This allows SoC developers to start design (flow setup and cleanup) and provide feedback earlier, significantly reducing overall cycle time. We propose an optimized approach for generating these preliminary views, achieving up to 40% faster runtime and minimizing delays caused by human intervention. This streamlined technique allows for faster iterations and feedback, increasing development speed and competitiveness in the competitive industry.
Event Type
Engineering Track Poster
TimeTuesday, June 255:14pm - 5:15pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP