Presentation
AI-Powered High-Sigma Automated Full Library Verification Methodology for Standard Cells
DescriptionThis paper addresses the critical challenge in chip design scalability, where standard cells are replicated in the millions, resulting in designs with tens of billions of transistors. Traditional methods of constraining Process, Voltage, and Temperature (PVT) corners based on past experiences and conducting Monte Carlo simulations on worst-case scenarios prove unreliable. Incorrectly predicting worst-case PVT can lead to schedule delays and design robustness issues. The brute-force Monte Carlo methods for high sigma verification are both costly and impractical.
To overcome these challenges, we present an AI-powered automated methodology for detecting and verifying worst-case yield. Our single-pass PVT + variation high-sigma solution, exemplified by the Solido PVTMC Verifier, achieves the fastest runtime, while the brute-force accurate high-sigma solution, demonstrated by Solido High-Sigma Verifier, ensures the highest accuracy.
The results on latch-based D flip-flop circuits showcase the effectiveness of our approach. Solido High-Sigma Verifier verified bimodality failure occurrences with 4,000 simulations, delivering a staggering 2,500,000X faster runtime than brute-force methods. Furthermore, the yield for this cell at the target PVT was verified to 6.322 sigma, accompanied by a remarkable 30X runtime speedup compared to the previous methodology. This signifies not only improved performance but also better accuracy and coverage rates.
To overcome these challenges, we present an AI-powered automated methodology for detecting and verifying worst-case yield. Our single-pass PVT + variation high-sigma solution, exemplified by the Solido PVTMC Verifier, achieves the fastest runtime, while the brute-force accurate high-sigma solution, demonstrated by Solido High-Sigma Verifier, ensures the highest accuracy.
The results on latch-based D flip-flop circuits showcase the effectiveness of our approach. Solido High-Sigma Verifier verified bimodality failure occurrences with 4,000 simulations, delivering a staggering 2,500,000X faster runtime than brute-force methods. Furthermore, the yield for this cell at the target PVT was verified to 6.322 sigma, accompanied by a remarkable 30X runtime speedup compared to the previous methodology. This signifies not only improved performance but also better accuracy and coverage rates.
Presenters
Event Type
Front-End Design
TimeWednesday, June 2610:30am - 10:48am PDT
Location2010, 2nd Floor
AI
Design
Engineering Tracks
Front-End Design