Presentation
Improving Power Efficiency using Workload-aware PPA Analysis for AI Engine
DescriptionWith the increasing demand of AI and ML applications, the need for specialized hardware designs becomes imperative to achieve high performance and energy efficiency in computing. Our AI Engines (AIE) are developed to proficiently accelerate such workloads, particularly for complex ML models with competitive energy efficiency. For the energy efficient computing in AIE, we developed a workload-aware power analysis methodology to push the limits of PPA targets, and started Shift Left at the early stage of RTL design for AIE in Ryzen, Epyc and Versal product families. The framework includes power vector generation, automatic workload selection, power report analysis, creation of power model at RTL level. In addition to the early power estimations for design changes at RTL level, it generates AIE core pipeline instruction statistics used in AIE advanced power modeling training procedure and other valuable information such as data dependencies that can increase accuracy of power model. We observed that dynamic power and CG related metric WCPP were significantly improved by average 27% and 56% respectively, throughout the AIE IP design developments.
Event Type
Front-End Design
TimeWednesday, June 2610:48am - 11:06am PDT
Location2010, 2nd Floor
AI
Design
Engineering Tracks
Front-End Design