Presentation
Fast and Deterministic Memory Yield Estimation Using Machine Learning Augmented Statistical Simulations
DescriptionWith ever-shrinking CMOS technology, particularly in nanometer regime, when devices are operating at ultra-low voltages, device variation poses major challenge for SRAM designs that use smallest feature devices. Achieving good yield on silicon requires very high sigma qualification (>6-sigma) based on the application and total capacity used in the SoC. Existing CAD solutions mostly rely on methodologies such as importance sampling or extreme value distribution (EVD). These methodologies suffer from inaccuracies and are not feasible for larger circuits. Further, non-gaussian nature of variations puts a hard limitation on such methodologies.
In this work, we have demonstrated the precise yield estimation using HSMC and DSVC available in synopsys AVA suite. This methodology is using machine-learning algorithm to precisely evaluate n-sigma measurements even for larger circuits (~2k MOS). We identify the dominant blocks in memory for variation such as bitcell, sense-amplifier and wordline underdrive circuit. HSMC and DSVC help to capture n-sigma distant behaviour for these blocks. Replacing these blocks by their m-sigma equivalent spice models in full memory instance helps to analyze n-sigma full entity qualification even in a nominal simulation, thus avoiding the need of statistical simulation at full memory instance. This methodology helps to reduce turn-around time for this analysis from ~2 weeks to ~1 day.
In this work, we have demonstrated the precise yield estimation using HSMC and DSVC available in synopsys AVA suite. This methodology is using machine-learning algorithm to precisely evaluate n-sigma measurements even for larger circuits (~2k MOS). We identify the dominant blocks in memory for variation such as bitcell, sense-amplifier and wordline underdrive circuit. HSMC and DSVC help to capture n-sigma distant behaviour for these blocks. Replacing these blocks by their m-sigma equivalent spice models in full memory instance helps to analyze n-sigma full entity qualification even in a nominal simulation, thus avoiding the need of statistical simulation at full memory instance. This methodology helps to reduce turn-around time for this analysis from ~2 weeks to ~1 day.
Event Type
IP
TimeTuesday, June 2511:00am - 11:15am PDT
Location2010, 2nd Floor
Engineering Tracks
IP