Presentation
Use UVM for AMS DFT through IEEE 1687 Procedural Description Language
SessionAdvanced Verification
DescriptionTime to market and bug free chip has put lot of pressure on the verification domain and resulted into multiple verification techniques that complement each other. UVM is reusable and robust verification environment. AMS verification tests cases can be integrally fused in UVM and design module description at random abstraction level that allows effective verification test setup. In this paper, we shall discuss how we have extended the existing IEEE1687 flow to support analog signals. Than we talk about the approach with which verification engineer can effectively reuse DFT test cases described in the IEEE 1687 Procedural Description Language (PDL). PDL is suited to describe the digital setup of an AMS test and is written at IP level. It does guarantee a path to any production test system therefore it is used to describe the AMS test cases as an input for DFT Verification. The approach has the potential to improve the quality of DFT test cases and shall improve the overall code coverage of the AMS design.
Event Type
Front-End Design
TimeTuesday, June 251:30pm - 1:45pm PDT
Location2010, 2nd Floor
Design
Engineering Tracks
Front-End Design