Presentation
Automated Design Scenario Extraction From A Large Design For Faster Debug Of Static Verification Tools
DescriptionIn recent times, Increased size of SOC has made static verification time and memory consuming. In a SOC which contains billions of design elements, few cases of missing/false violations or large run time issues get reported by customer on any static tool. When such issues get reported at the time of final sign off stage of the chip, they become a gating issue for any static tool. In such case static tool vendors are expected to provide the fix in the tool on urgent priority.
To fix any issue in the tool R&D engineer need to first identify root cause of the issue. Below methods are the traditional ways of root cause identification in a big design:
1. Using debug prints
2. Apply debugger on code execution
3. Code profiling tools
4. Reducing the size of design by making unrelated portion of design as Blackbox model
Finding the root cause of the issue using above mentioned ways and provide quick fix in tool takes time as:-
R&D, AE may not have direct access to design.
Shipping design to a secure network is difficult or takes time
High number of debug prints make it difficult to find root cause
Attaching debuggers on large design is cumbersome and slow
From the debug fields in violations and other reports, R&D or field only has limited knowledge about the design scenarios. It is difficult to create a unit reproducer
It has often been observed that having a small reproducer in hand reduces the turnaround time significantly for delivery of the fix. To overcome this challenge we have developed an utility in our tool which provides us a capability to create a small reproducer out of the big design.
To fix any issue in the tool R&D engineer need to first identify root cause of the issue. Below methods are the traditional ways of root cause identification in a big design:
1. Using debug prints
2. Apply debugger on code execution
3. Code profiling tools
4. Reducing the size of design by making unrelated portion of design as Blackbox model
Finding the root cause of the issue using above mentioned ways and provide quick fix in tool takes time as:-
R&D, AE may not have direct access to design.
Shipping design to a secure network is difficult or takes time
High number of debug prints make it difficult to find root cause
Attaching debuggers on large design is cumbersome and slow
From the debug fields in violations and other reports, R&D or field only has limited knowledge about the design scenarios. It is difficult to create a unit reproducer
It has often been observed that having a small reproducer in hand reduces the turnaround time significantly for delivery of the fix. To overcome this challenge we have developed an utility in our tool which provides us a capability to create a small reproducer out of the big design.
Event Type
IP
TimeTuesday, June 252:00pm - 2:15pm PDT
Location2012, 2nd Floor
Engineering Tracks
IP