Presentation
Considering Selective Resistance Extraction for Performance & Accuracy Trade-off for Memory IP Simulation
DescriptionCustom memories are used in wide spectrum of applications and hence support many features that are useful at the SOC level. The number of combinations for verifying such functional behaviors, physical parameters and operating variations are huge and can impact the turn-around time of development due to high simulation run-time.
For large IPs like memories, leafcell extraction is done using Cc (only capacitance) methodology for supply lines and RCc (both resistance and capacitance) methodology for signals to reduce extraction size and gain in simulation run-time at the cost of accurate consideration of voltage drop at the supply lines. With advancing technologies, the cumulative effect of lowered supply voltages, increased voltage drop due to contact resistance leads to higher device sensitivity and lower noise margin. If ignored this can lead to a parametric yield loss.
For accurate characterization and robustness, we propose a methodology using layer information and StarReducer tool which helps consider voltage drop in supply lines due to contact resistance effectively. The timing penalty of around 4% between current and accurate methodology reduces to 1% using proposed methodology providing a fine balance between accuracy and simulation run time which helps in design and validation phase.
For large IPs like memories, leafcell extraction is done using Cc (only capacitance) methodology for supply lines and RCc (both resistance and capacitance) methodology for signals to reduce extraction size and gain in simulation run-time at the cost of accurate consideration of voltage drop at the supply lines. With advancing technologies, the cumulative effect of lowered supply voltages, increased voltage drop due to contact resistance leads to higher device sensitivity and lower noise margin. If ignored this can lead to a parametric yield loss.
For accurate characterization and robustness, we propose a methodology using layer information and StarReducer tool which helps consider voltage drop in supply lines due to contact resistance effectively. The timing penalty of around 4% between current and accurate methodology reduces to 1% using proposed methodology providing a fine balance between accuracy and simulation run time which helps in design and validation phase.
Event Type
IP
TimeTuesday, June 2510:45am - 11:00am PDT
Location2010, 2nd Floor
Engineering Tracks
IP