Presentation
PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency
DescriptionHuffman decoding is crucial in data compression, and the self-synchronization-based parallel decoding algorithm enables subsequence-level parallelism. This paper introduces PHD, the first accelerator designed for self-synchronization-based parallel Huffman decoding on the Field-Programmable Gate Array (FPGA). Designing PHD poses challenges, including managing fine-grained parallelism, addressing limited on-chip memory, and handling inter-codeword dependency. PHD incorporates bit-level, subsequence-level, and tile-level parallelism, utilizes hybrid memory to store the codebook efficiently, and introduces the ONCE MORE optimization to reduce decoding loop iterations. Experimental results demonstrate that PHD outperforms the state-of-the-art GPU-based baseline regarding latency (9.4X to 12.8X reduction) and energy consumption (12.4X to 18.2X reduction).
Event Type
Research Manuscript
TimeWednesday, June 264:45pm - 5:00pm PDT
Location3003, 3rd Floor
Design
SoC, Heterogeneous, and Reconfigurable Architectures