Presentation
Chiplever: Towards Effortless Extension of Chiplet-based System for FHE
DescriptionFully Homomorphic Encryption (FHE) is one of the most promising privacy-preserving techniques, which has drawn increasing attention from both academia and industry due to its ideal security. Chiplet-based designs integrate multiple dies (chiplet) into the package delivering high performance and thereby are embraced by the resources-hungry FHE. Despite the chiplet-based system with various specialized accelerators, it falls short in supporting FHE due to the novel FHE polynomial operations. For a chiplet-based system that is not tailored for FHE, one common approach to make it capable of FHE is designing a new dedicated accelerator, However, this full design-and-build approach overlooks the existing abundant resources of accelerators in the system and thereby incurs repeated customization and resource waste.
In this paper, we propose Chiplever, a framework enables effortless extension of Chiplet-based system for FHE. We aim to fully harness the available resources in the room for efficient FHE. To achieve this, Chiplever (1)introduces a specialized extension in I/O Chiplet guided by semantics matching (2)and proposes an efficient allocator featuring specialized dataflow scheduling. (3)Chiplever provides three-step mapping to achieve compiler-level to hardware-level support for FHE and optimizes the data communications.
In this paper, we propose Chiplever, a framework enables effortless extension of Chiplet-based system for FHE. We aim to fully harness the available resources in the room for efficient FHE. To achieve this, Chiplever (1)introduces a specialized extension in I/O Chiplet guided by semantics matching (2)and proposes an efficient allocator featuring specialized dataflow scheduling. (3)Chiplever provides three-step mapping to achieve compiler-level to hardware-level support for FHE and optimizes the data communications.
Event Type
Research Manuscript
TimeWednesday, June 265:00pm - 5:15pm PDT
Location3003, 3rd Floor
Design
SoC, Heterogeneous, and Reconfigurable Architectures