Presentation
Accelerating Heterogeneous Workloads Using A Reconfigurable In-Memory Computing Architecture
DescriptionAs a small effort towards general purpose CIM paradigm, in this paper, we propose a heterogeneous workloads centric compute-in-memory (HWCCIM) architecture. Particularly, we present a design to compile essential algorithmic operations into an address table for in-memory computing circuits. Leveraging a reconfigurable address generation unit to guide data movement within different in-memory computing-based operator arrays, it is able to complete calculations and producing corresponding results. We further illustrate the construction of HWCCIM architecture in a behavioral-level circuit model. We also evaluate the proposed architecture using two classical algorithms, the Fast Fourier Transform (FFT) and the Multilayer Perceptron (MLP) algorithms. Compared to conventional approaches, HWCCIM achieves a maximum latency acceleration of 1.5x and an average latency acceleration of 1.3x.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
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