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HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks
DescriptionEmbedded Neural Networks (NNs) face significant challenges due to Single-Event Upsets (SEUs), compromising their reliability. To address this challenge, previous works study SEU layers sensitivity of AI models. Contrary to these techniques, remaining at high level, we propose a more accurate analysis, highlighting that, except for the last layer, faults transitioning from 0 to 1 significantly impact classification outcomes. Based on this specific behavior, we propose a simple hardware block able to detect and mitigate the SEU impact. Obtained results show that HTAG protection efficiency is near 96.85% for the LeNet-5 CNN inference model, suitable for an embedded system. This result can be improved with other protection methods for the classification layer. Additionally, it significantly reduces area overhead and critical path compared to existing approaches.
Event Type
Research Manuscript
TimeTuesday, June 2511:30am - 11:45am PDT
Location3012, 3rd Floor
Topics
Embedded Systems
Keywords
Time-Critical and Fault-Tolerant System Design