Presentation
GNN-assisted Back-side Clock Routing Methodology for Advance Technologies
DescriptionThe back-side metal layers exhibit lower parasitics compared to the front-side layers in advanced technologies, making them suitable for clock-net distribution. In this study, we explore the advantages of using back-side metal layers for clock routing, which is shared with a power delivery network. Our Graph Neural Network (GNN) based framework, effectively distributes the clock-tree between the front and back sides. We address the back-side clock nets' creation by incorporating back-side buffers. Our results demonstrate better clock and full-chip metrics represented by an increase of up to 13% in the effective frequency with equivalent power consumption, using 3 nm technology.
Event Type
Research Manuscript
TimeWednesday, June 264:30pm - 4:45pm PDT
Location3010, 3rd Floor
EDA
Physical Design and Verification