Presentation
DGR: Differentiable Global Router
DescriptionModern VLSI design flows necessitate fast and high-quality global routers. In this paper, we introduce DGR, a GPU-accelerated, differentiable global router capable of concurrent optimization for millions of nets, which we aim to open-source. Our innovation lies in the development of a routing Directed Acyclic Graph (DAG) forest to represent the 2D pattern routing space for all nets, enabling coordinated selection of Steiner trees and 2-pin routing paths from a global perspective. For efficient search within the DAG forest, we relax the discrete search space to be continuous and develop a differentiable solver accelerated by deep learning toolkits on GPUs. Experimental results demonstrate that DGR substantially mitigates routing overflow while concurrently reducing total wirelengths from 0.95% to 4.08% and via numbers from 1.28% to 2.54% in congested testcases compared to state-of-the-art academic global routers. Additionally, DGR exhibits favorable scalability in both runtime and memory with respect to the number of nets.
Event Type
Research Manuscript
TimeWednesday, June 264:45pm - 5:00pm PDT
Location3010, 3rd Floor
EDA
Physical Design and Verification