Presentation
Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing
DescriptionModern System-on-Chip (SoC) design is divided into hierarchical instances using the multiply-instantiated block (MIB) technique to simplify the design process. Top-level routing aims at providing routing prototyping between those instances. It requires consideration of replicated routing paths that can either be utilized for routing or remain as floating segments. Conventional path-searching based algorithm often fails to find a legal solution under such a scenario. To address this, we propose an effective and efficient top-level routing framework for MIBs by hashing the topology of each net and using a group maze routing scheme. Experimental results demonstrate promising performance compared to the winners of the MIB-aware top-level router contest 2022 organized by Synopsys.
Event Type
Research Manuscript
TimeWednesday, June 265:00pm - 5:15pm PDT
Location3010, 3rd Floor
EDA
Physical Design and Verification