Presentation
A High-Throughput, Energy-Efficient, and Constant-Time In-SRAM AES Engine with Massively-Parallel Bit-Serial Execution
DescriptionThis paper presents a high-throughput, energy-efficient, and constant-time in-SRAM Advanced Encryption Standard (AES) engine. The proposed in-memory AES ensures high-throughput operation exploiting the column-wise single instruction multiple data (SIMD) processing of compact round functions for both electronic-codebook (ECB) and counter (CTR) modes of operation. Moreover, we proposed a processor-assisted key loading strategy and a prudent memory management scheme to minimize the memory footprint needed for AES to improve the peak operating frequency and energy efficiency of the underlying compute SRAM hardware. The bit-serial processing further guarantees the constant-time execution of AES, providing strong resistance to side-channel timing attacks. Experimental results show that our proposed AES ECB design achieves 2.4×(149×) throughput, 2.4×(270×) throughput per area, 2.3×(7.7×) per block energy improvement as compared to the state-of-the-art non-constant-time (constant-time) designs, respectively. The resulted AES Counter (CTR) mode design achieves 1.9× per block energy improvement as compared to the state-of-the-art reconfigurable IMC AES CTR designs.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
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Design
EDA
Embedded Systems
IP
Security