Presentation
PONO: Power Optimization with Near Optimal SMT-based Sub-circuit Generation
DescriptionGenerating high-quality sub-circuit for local substitution is an effective optimization technique in logic synthesis. There have been abundant works on generating area and delay optimal sub-circuits, greatly enhancing the logic optimization quality. However, power- oriented sub-circuit generation is rarely discussed, while optimizing power consumption in this sub-15 nm era is of paramount interest. We propose PONO, an SMT-based near optimal sub-circuit generation flow for power optimization. PONO enables power-oriented circuit library building and fills the gap in generating circuits near the Pareto frontier in PPA (Power, Performance, and Area). It manifests superiority in power reduction over traditional one in rewrite, a key logic optimization algorithm. We test PONO on EFPL benchmarks, and it shows 8.7% less power consumption with comparable performance and area after placement and routing.
Event Type
Research Manuscript
TimeTuesday, June 252:45pm - 3:00pm PDT
Location3004, 3rd Floor
EDA
RTL/Logic Level and High-level Synthesis