Presentation
LEAP: Layout aware Estimation of Analog design Parasitics
DescriptionThe field of analog custom design faces significant challenges during layout generation due to its inherent complexity, slow execution, and propensity for errors. These issues are further exacerbated due to aggressive technology scaling within advanced process nodes. The performance of analog designs is highly sensitive to layout parasitics, underscoring the critical need for accurate parasitic estimation during all design stages, including schematic design, placement, and routing. This necessity stems from the direct impact of parasitics on key performance metrics such as device performance, IR drop, power consumption, and node voltage stability. This paper presents a novel methodology that employs transformer convolution based GNN architecture and integer linear programming (ILP) optimization techniques, to predict key layout parasitics for analog circuits. Our approach is distinct in its ability to comprehensively model capacitance and resistance parasitics in a scalable hierarchical tree structure. Through our novel parasitic modeling framework, we demonstrate on advanced sub-10nm process technology, a mean-average-percentage-error (MAPE) of 11% and 11.5% for point-to-point resistance and lumped capacitance estimation respectively. Using the estimated RC models, we were able to reduce the gap between pre and post layout simulation design metrics by a factor of 3X on industrial designs.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
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