Presentation
Knowing The Spec to Explore The Design via Transformed Bayesian Optimization
DescriptionAI chip scales expediently in the large language models (LLMs) era. In contrast, the existing chip design space exploration methods, aimed at discovering optimal yet often infeasible or unproduceable Pareto-front designs, are hindered by neglect of design specifications. In this paper, we propose a novel Spec-driven transformed Bayesian optimization framework to find expected optimal RISC-V SoC architecture designs for LLM tasks. The highlights of our framework lie in a tailored transformed Gaussian process (GP) model prioritizing specified target metrics and a customized acquisition function (EHRM) in multi-objective optimization. Extensive experiments on large-scale RISC-V SoC architecture design explorations for LLMs, such as Transformer, BERT, and GPT-1, demonstrate that our method not only can effectively find the design according to QoR values from the spec, but also outperforms 34.59% in ADRS over previous state-of-the-art approach with 66.67% runtime.
Event Type
Research Manuscript
TimeTuesday, June 252:45pm - 3:00pm PDT
Location3010, 3rd Floor
EDA
RTL/Logic Level and High-level Synthesis