Session
HLS & Emerging Techniques for Synthesis
Session Chairs
DescriptionThis session focuses on applying innovative methods in logic synthesis and HLS (high-level synthesis) of circuits. The first two papers work on memory partitioning and dynamic memory management in HLS to improve performance. The third and fourth papers present interesting methods to assist RTL debug and to make effective synthesis for superconducting circuits. The last two papers apply innovative VAE (variational autoencoder) and Bayesian Optimization to design and optimize circuits.
Event TypeResearch Manuscript
TimeTuesday, June 251:30pm - 3:00pm PDT
Location3010, 3rd Floor
EDA
RTL/Logic Level and High-level Synthesis
Presentations
| 1:30pm - 1:45pm PDT | PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis | |
| 1:45pm - 2:00pm PDT | High-Performance and Resource-Efficient Dynamic Memory Management in High-Level Synthesis | |
| 2:00pm - 2:15pm PDT | Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue | |
| 2:15pm - 2:30pm PDT | Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic | |
| 2:30pm - 2:45pm PDT | CircuitVAE: Efficient and Scalable Latent Circuit Optimization | |
| 2:45pm - 3:00pm PDT | Knowing The Spec to Explore The Design via Transformed Bayesian Optimization |