Presentation
Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic
DescriptionGate-level clocking, typical in traditional approaches to Single Flux Quantum (SFQ) technology, makes the effective synthesis of superconducting circuits a significant engineering hurdle. This paper addresses this challenge by employing the recently introduced xSFQ logic family. xSFQ leverages dual-rail alternating encoding to eliminate the clock dependency from the superconducting gate semantics. This obviates the need for ad hoc modifications to existing synthesis tools and avoids unnecessary circuit resource overheads, marking a significant advancement in superconducting circuit design automation. Our implementation results demonstrate an average reduction of over 80% in the Josephson junction count for circuits from the ISCAS85, EPFL, and ISCAS89 benchmark suites.
Event Type
Research Manuscript
TimeTuesday, June 252:15pm - 2:30pm PDT
Location3010, 3rd Floor
EDA
RTL/Logic Level and High-level Synthesis