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Presenter

Sreekanth Rajan
Ansys
Presentations
Engineering Track Poster
A Closed Loop IR and Timing Comprehensive Co-Signoff Methodology
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Shift-left Solution for Enhancing Power Integrity in physical design construction with RedHawk-Fusion
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Redefining Hierarchical Power Integrity signoff for Ultra-Large System-on-Chips
Back-End Design
Embedded Systems
Front-End Design
IP