Presentation
Redefining Hierarchical Power Integrity signoff for Ultra-Large System-on-Chips
DescriptionModern SoCs, with billions of transistors, pose challenges for traditional power integrity signoff due to increased node counts and process scaling. The existing methods are time-consuming, require substantial resources, and often result in systematic inaccuracies. To address this, a bottom-up hierarchical signoff methodology is proposed, which allows block-level signoff and reduces the overall turnaround time without compromising accuracy. This approach leverages the RedHawk-SC tool by Ansys to create child block models that are instantiated at the next hierarchical level. The hierarchical modeling flow has shown a performance improvement of ~45-50% during block level runs, with an accuracy within a 5% range compared to flat runs. The methodology is under continuous improvement to enhance accuracy and efficiency. The next step involves implementing a Hierarchical SignalEM methodology using the same reduced model solution.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP