Presentation
Shift-left Solution for Enhancing Power Integrity in physical design construction with RedHawk-Fusion
Description· With shrinking process node, dynamic voltage drop becomes an increasingly challenging issue, due to the increased silicon frequency and reduced voltage headroom.
· Advance tech nodes also have more resistive power grid (PG). Combination of PG complexity and design size increase is making designs more difficult for IR closure.
· Turn-around time for the construction flow also has kept increasing, which adds more pressure on the IR closure. With all of these above, it becomes essential to have an efficient shift-left methodology to improve the productivity of IR fixing.
· Traditionally IR fixing has been done manually in post-route stage due to lack of an integrated in-construction automation. In this work, a methodology is proposed to utilize various power integrity solutions in Redhawk-Fusion EDA tool to perform in-design IR analysis and automated fixing during construction.
With the proposed solution, satisfactory IR violations reduction was observed (67% dynamic/100% static in our test cases). Significant turn-around time and eco iteration loops reduction for EM/IR convergence is achieved.
· Advance tech nodes also have more resistive power grid (PG). Combination of PG complexity and design size increase is making designs more difficult for IR closure.
· Turn-around time for the construction flow also has kept increasing, which adds more pressure on the IR closure. With all of these above, it becomes essential to have an efficient shift-left methodology to improve the productivity of IR fixing.
· Traditionally IR fixing has been done manually in post-route stage due to lack of an integrated in-construction automation. In this work, a methodology is proposed to utilize various power integrity solutions in Redhawk-Fusion EDA tool to perform in-design IR analysis and automated fixing during construction.
With the proposed solution, satisfactory IR violations reduction was observed (67% dynamic/100% static in our test cases). Significant turn-around time and eco iteration loops reduction for EM/IR convergence is achieved.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP