Presentation
A Closed Loop IR and Timing Comprehensive Co-Signoff Methodology
DescriptionTraditionally, the budgeting of STA and IR drop limits was done separately, with each converging to their respective limits without much interaction. Recently, there have been attempts to incorporate IR drop into STA analysis for a more informed timing signoff. However, the reverse - incorporating timing critical path into IR signoff - has not been as thoroughly investigated.
This work proposed a methodology for IR drop signoff with awareness of timing critical paths. It utilizes the latest features from the Redhawk-SC EDA tool to incorporate timing analysis results into IR voltage drop signoff. This IR voltage drop data can subsequently be incorporated into an incremental timing analysis to pinpoint potential waivers for IR violations. Evaluation data from real design blocks in advanced nodes demonstrate that it can improve design coverage and enhance silicon robustness and system performance.
This work proposed a methodology for IR drop signoff with awareness of timing critical paths. It utilizes the latest features from the Redhawk-SC EDA tool to incorporate timing analysis results into IR voltage drop signoff. This IR voltage drop data can subsequently be incorporated into an incremental timing analysis to pinpoint potential waivers for IR violations. Evaluation data from real design blocks in advanced nodes demonstrate that it can improve design coverage and enhance silicon robustness and system performance.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP