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Presenter

Yibo Lin
Peking University
Presentations
Research Manuscript
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning
EDA
Timing and Power Analysis and Optimization
Research Manuscript
PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis
EDA
Analog CAD, Simulation, Verification and Test
Research Manuscript
Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation
AI
Design
AI/ML Architecture Design
Research Manuscript
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs
EDA
Physical Design and Verification
Research Manuscript
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Work-in-Progress Poster
An Effective Timing Driven Placement with Accurate Differentiable Timing Approximation Integration
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Research Manuscript
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration
Design
In-memory and Near-memory Computing Circuits
Research Manuscript
Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing
EDA
Physical Design and Verification
Chair of Sessions
Research Manuscript
Racing Against Time: Innovations in Timing
EDA
Timing and Power Analysis and Optimization