Presentation
TSV KOZ separation 3DIC P&R area optimization methodology considering device impact by TSV
DescriptionTSVs affect surrounding devices, causing device performance and reliability to vary within several micrometers of the TSV.
TSVs affect the saturation current (Idsat) of NMOS and PMOS devices, which can be interpreted as the variation of FET's Idsat with distance and divided into Soft KOZ and Hard KOZ.
In Hard KOZ, the placement of DVC and routing of metal are prohibited as the impact of DVC performance is large.
In Soft KOZ, the placement and routing of standard cells are allowed as the impact of TSV stress on the device can be predicted.
The timing impact of cells within the KOZ is reflected in the timing analysis.
When the proposed KOZ method is applied, the area of the KOZ decreases by 4.58% compared to the reference. The cell area decreases by 2.86%, resulting in a 7.44% decrease in the overall block area.
The speed of the top 300 critical paths at the block level is degraded by 0.16%.
TSVs affect the saturation current (Idsat) of NMOS and PMOS devices, which can be interpreted as the variation of FET's Idsat with distance and divided into Soft KOZ and Hard KOZ.
In Hard KOZ, the placement of DVC and routing of metal are prohibited as the impact of DVC performance is large.
In Soft KOZ, the placement and routing of standard cells are allowed as the impact of TSV stress on the device can be predicted.
The timing impact of cells within the KOZ is reflected in the timing analysis.
When the proposed KOZ method is applied, the area of the KOZ decreases by 4.58% compared to the reference. The cell area decreases by 2.86%, resulting in a 7.44% decrease in the overall block area.
The speed of the top 300 critical paths at the block level is degraded by 0.16%.
Event Type
Back-End Design
TimeMonday, June 2410:25am - 10:40am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks