Presentation
ML based PPA Push using DRV Prediction
DescriptionAs process technologies keep on advancing, longer physical design time with more iteration is required Longer physical design time with more iteration makes hard to push PPA to limit. DRV(Design Rule Violation) is not know until before detail routing, which is most time-consuming process, and it is hard to fix it after detail routing by routing alone and cell placement need to be modified. GRC(Global Routing Congestion), can no longer directly correlate the DRVs after detailed routing, what makes detailed routing necessary to verify whether DRVs occurs due to current placement in advanced process even though it is time consuming process To reduce physical design time, predict DRVs with fast runtime and moderate accuracy is required to modify cell placement before running detailed routing.
Event Type
Back-End Design
TimeMonday, June 2410:40am - 10:55am PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks