Presentation
A Systematic Approach to 3D Cutline Exploration and Benchmarking
DescriptionAs wafer cost continues to increase at a rapid pace, there is a growing demand to convert more of our 2D SoCs into 3D System-In-Package designs. Furthermore, as individual IPs get larger and more complex, we see a need to disaggregate these designs along arbitrary boundaries, or "cutlines", rather than along standard fabric interfaces as has been done in the past. This results in large numbers of high-speed ad hoc interfaces on the die boundaries and creates a need for cross-die optimization techniques. Silicon architects and floorplanners need robust and intuitive methods to rapidly create and assess different configurations in the early planning phase of the design, so that they can deliver the best mix of Performance, Power, Area and Cost for the product. This paper presents these construction and analysis techniques on 2 different designs – a low-power Crypto core that explores several cutlines, and a high-speed compute module that explores different bump pitch and floorplan options. We present exhaustive studies and KPIs that can support cutline decisions, including 2D/3D PPA comparison, 3D IR/Thermal plots, 2D vs 3D QoR (ex. buffer/inverter count & routing length), D2D Bump-to-Flop distance monitoring, D2D timing paths analysis, and 2D vs 3D metal layer usage.
Presenters
Event Type
Back-End Design
TimeMonday, June 242:24pm - 2:42pm PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks