Presentation
Globalized bulk biasing based substrate noise reducing method for size reduction in digital circuit
DescriptionTechnology scaling results in smaller die size with increased amount of bulk-biasing penalty. In this paper, we propose a physical synthesis methodology for digital circuit that minimizes the overhead. Considering bulk-biasing constraint of mutual distance and density, we first place global bulk-biasing active before standard cell placement. Then, to guarantee the biasing constraints, we transform the placement using slide-window algorithm. For 3D V-NAND digital design [1], measurement result showed 7.2% of area reduction compared to the conventional methodology.
[1] M. Kim et al., "A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface," ISSCC 2022:136-137.
[1] M. Kim et al., "A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface," ISSCC 2022:136-137.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP