Presentation
Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
DescriptionOur objective is to exhaustively verify static and dynamic connections, from the IPs deep inside an FPGA "core," all the way t the outer perimeter of an AI-centric computational circuit boards. The circuits usually have FPGAs from different vendors, many configurations, pinouts, implementation constraints which lead to high risk of connection bugs.
The simulation approach is not working for our multiple variants of large-scale, complex FPGA-based, AI-centric cloud hardware designs to meet our tight schedule, since it requires weeks of manual testbench development, weeks of run and turnaround time, and it is not exhaustive, and bugs can escape.
Formal connectivity verification establishes a framework for both experts and non-experts alike that ensures simplicity, reusability, and scalability, from block-to-system level, static and dynamic connectivity verification. It provides a comprehensive exposition of the design hierarchies required by backend physical tools, provides visibility into hidden cone of logic uncovering "blind spots" that escape detection in simulation-based techniques, and exhaustively proves connections when no stimulus can violate them.
With formal verification, we successfully uncovered RTL bugs in minutes - a task that weeks of simulation-based regressions had failed to accomplish. We got huge boost in productivity - 95% savings in engineer's time!
The simulation approach is not working for our multiple variants of large-scale, complex FPGA-based, AI-centric cloud hardware designs to meet our tight schedule, since it requires weeks of manual testbench development, weeks of run and turnaround time, and it is not exhaustive, and bugs can escape.
Formal connectivity verification establishes a framework for both experts and non-experts alike that ensures simplicity, reusability, and scalability, from block-to-system level, static and dynamic connectivity verification. It provides a comprehensive exposition of the design hierarchies required by backend physical tools, provides visibility into hidden cone of logic uncovering "blind spots" that escape detection in simulation-based techniques, and exhaustively proves connections when no stimulus can violate them.
With formal verification, we successfully uncovered RTL bugs in minutes - a task that weeks of simulation-based regressions had failed to accomplish. We got huge boost in productivity - 95% savings in engineer's time!
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP