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Organization

Microsoft
Contributors
Kiran Adhikari
Eustace Asanghanwa
Erik Berg
Amit Garg
Onkar Hule
Piyush Jain
Medha Kulkarni
Medha Kulkarni
Amit Kumar
Brad Lackey
Nguyen Le
Serge Leef
Rossana Liu
Rossana Liu
Linh Nguyen
Pranav Ranganathan
Pranav Ranganathan
Martin Sanchez
Preetish Singha
Apurva Soni
Karthikk Sridharan
Chip Stratakos
Chip Stratakos
Amber Telfer
Benjamin Ting
Joe Tostenrude
Joe Tostenrude
Prashant Varshney
Hailang Wang
Hailang Wang
Presentations
Engineering Track Poster
A Closed Loop IR and Timing Comprehensive Co-Signoff Methodology
Back-End Design
Embedded Systems
Front-End Design
IP
Front-End Design
AI co-pilot: Exploring the AI Frontier in Chip Design
AI
Design
Engineering Tracks
Front-End Design
Tutorial
Deep Dive in Foundry Process Design Kits (PDKs)
EDA
Embedded Systems and Software
Edge Intelligence & GenAI: Exploring Challenges and Ethics
AI
Embedded Systems
Engineering Tracks
Research Panel
Generative AI for Chip Design: Game Changer or Damp Squib?
AI
EDA
Engineering Track Poster
Microsoft's Comprehensive IP Handoff Flow
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Next-Gen comprehensive IR analysis with Ansys SigmaAV
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Overcoming Collaboration Hurdles in High-Tech Product Development with Keysight tool on Azure infrastructure.
Back-End Design
Embedded Systems
Front-End Design
IP
Research Panel
Quantum Computing: Accomplishments, Bottlenecks, and Timelines
Design
Quantum Computing
Engineering Track Poster
Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Redefining Hierarchical Power Integrity signoff for Ultra-Large System-on-Chips
Back-End Design
Embedded Systems
Front-End Design
IP
Exhibitor Forum
Secure Collaboration Across Enterprises on the Cloud
Hands-On Training Session
Setting up a secure, turn-key cloud-based engineering environment for semiconductor development, collaboration and debug with Azure Modeling and Simulation Workbench.
Engineering Track Poster
Shift-left Solution for Enhancing Power Integrity in physical design construction with RedHawk-Fusion
Back-End Design
Embedded Systems
Front-End Design
IP
Exhibitor Forum
Understanding SigmaDVD – Ansys’ Radical New Methodology for Voltage Drop Signoff