Presentation
Leveraging several automated techniques and methodologies for faster coverage closure and design sign-off
DescriptionBottlenecks in Design verification sign-off process during project execution:
1. Coverage closure
2. Regression management
Problems faced during Coverage closure :
1. Multiple iterations of regressions
2. Covering all the bins (Lakhs of bins in current RTL designs)
3. Analyzing the uncovered bins
The motivation for writing this paper is to create awareness and introduce the automated techniques which saves iterations and execution time of DV engineer and make his life easier with reduced efforts for closing coverage
The presentation explains several such techniques and along the way also mentions different best practices that need to be followed within the test bench infrastructure for faster coverage and regression closure and also to catch the maximum number of bugs.
Leveraging Portable stimulus standard (PSS) for faster functional coverage closure and constraints offloading.
1. Coverage closure
2. Regression management
Problems faced during Coverage closure :
1. Multiple iterations of regressions
2. Covering all the bins (Lakhs of bins in current RTL designs)
3. Analyzing the uncovered bins
The motivation for writing this paper is to create awareness and introduce the automated techniques which saves iterations and execution time of DV engineer and make his life easier with reduced efforts for closing coverage
The presentation explains several such techniques and along the way also mentions different best practices that need to be followed within the test bench infrastructure for faster coverage and regression closure and also to catch the maximum number of bugs.
Leveraging Portable stimulus standard (PSS) for faster functional coverage closure and constraints offloading.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP