Presentation
The Designer's Superpower! Early Circuit Verification with Calibre nmLVS Recon
DescriptionIncreasing complexity in integrated circuits (ICs) node over node results significant growth in circuit verification time and effort. Today's tapeout sensitivities make it critical to begin checking and fixing connectivity issues in earlier design stages, since connectivity violations will affect downstream flows such as reliability verification (PERC/ESD-checks), electromigration/voltage drop (EMIR) layout optimization. However, running signoff verification in early stages typically produces thousands, if not millions, of layout errors, only some of which are actionable. Addressing all these errors is an unproductive drain on both time and resources, as many will simply disappear when full-chip design comes together at signoff, while finding and debugging relevant errors requires a significant number of iterations and many manual steps. Critical pain points in early design stage circuit verification include short isolation (SI), electrical rule checking (ERC), and soft connection checking (Softchk). The Calibre nmLVS Recon tool is specifically designed to improve early-stage layout vs. schematic (LVS) verification providing targeted functionalities to address these issues. Earlier focused circuit verification reduces overall IC design verification and debugging time while improving design quality and time to market, without compromising the signoff quality. Real-world results demonstrate the effectiveness and efficiency of the Calibre nmLVS Recon tool.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP