Presentation
A Novel methodology for re-simulation of block vectors helping validate Power Optimization QoR 20x faster
DescriptionTo achieve the highest power savings, it is desired to make modification as early as possible in the design cycle requiring RTL Power Optimization flows. One of the major challenges with RTL Power Optimization is lack of eco-system to validate the impact on Power for the changes. To capture the power saving for modifications, new waveform must be generated, requiring a re-simulation. In most cases the simulation setup is available for SoC, thus doing the re-simulation for modified RTL becomes resource and time-consuming process.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP