Presentation
Peak Power Optimization using Active Datapath Operator Profiling
DescriptionPower estimation has become a critical metric for design evaluation and thus the focus now is on both Average and Peak Power. Using strategies like Clock-Gating, to reduce the average power may also reduce peak power. With focus on average power, the strategies which reduced peak power with no or minor impact on the average power are often not used. Neglecting high peak power can lead to increase in cost of packaging or even failure.
In this paper, we propose peak power optimization technique by re-scheduling data path operators across cycles. Cycle Accurate Peak Power at RTL was used to identify the peak power region using RTL-PA tools e.g. PowerPro. Waveform reconstruction using recon engine was used to generate active operator profile for the identified region. Based on the knowledge of active operators causing peak power, the RTL was hand modified and checked for correctness using formal verification tools. The Cycle Accurate Peak Power for the modified RTL was performed to validate the impact on Peak Power.
From the results it is clearly visible that same functionality of RTL was achieved with lower peak power. There was no noticeable impact on the average power of the design.
In this paper, we propose peak power optimization technique by re-scheduling data path operators across cycles. Cycle Accurate Peak Power at RTL was used to identify the peak power region using RTL-PA tools e.g. PowerPro. Waveform reconstruction using recon engine was used to generate active operator profile for the identified region. Based on the knowledge of active operators causing peak power, the RTL was hand modified and checked for correctness using formal verification tools. The Cycle Accurate Peak Power for the modified RTL was performed to validate the impact on Peak Power.
From the results it is clearly visible that same functionality of RTL was achieved with lower peak power. There was no noticeable impact on the average power of the design.
Event Type
Engineering Track Poster
TimeTuesday, June 255:44pm - 5:45pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP